1. Field of the Invention
This invention relates generally to semiconductor products manufacturing, and, more particularly, to a method and apparatus for programming latency for improving wafer-to-wafer uniformity.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today""s manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Among the factors that affect semiconductor device manufacturing are wafer-to-wafer variation that are caused by manufacturing problems that include start-up effects of manufacturing machine tools, memory effects of manufacturing chambers, and first-wafer effects. One of the process steps that are adversely affected by such factors is the photolithography overlay process. Overlay is one of several important steps in the photolithography area of semiconductor manufacturing. Overlay control involves measuring the misalignment between two successive patterned layers on the surface of a semiconductor device. Generally, minimization of misalignment errors is important to ensure that the multiple layers of the semiconductor devices are connected and functional. As technology facilitates smaller critical dimensions for semiconductor devices, the need for reduced of misalignment errors increases dramatically.
Generally, photolithography engineers currently analyze the overlay errors a few times a month. The results from the analysis of the overlay errors are used to make updates to exposure tool settings manually. Some of the problems associated with the current methods include the fact that the exposure tool settings are only updated a few times a month. Furthermore, currently the exposure tool updates are performed manually.
Generally, a set of processing steps is performed on a lot of wafers on a semiconductor manufacturing tool called an exposure tool or a stepper. The manufacturing tool communicates with a manufacturing framework or a network of processing modules. The manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which the stepper is connected, thereby facilitating communications between the stepper and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process. The input parameters that control the manufacturing process are revised periodically in a manual fashion. As the need for higher precision manufacturing processes are required, improved methods are needed to revise input parameters that control manufacturing processes in a more automated and timely manner. Furthermore, wafer-to-wafer manufacturing variations can cause non-uniform quality of semiconductor devices.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided for implementing programmed latency for improved wafer-to-wafer uniformity. Semiconductor devices for wafer-by-wafer analysis are identified. At least one value of a controlled variable in the wafer-by-wafer analysis is identified. A trajectory of recipes for the identified semiconductor devices is created. A sequence analysis of wafer-to-wafer variations is performed using the trajectory of recipes upon the identified semiconductor devices. A latency control is performed in response to the sequence analysis. A feed-forward implementation of wafer-by-wafer latency control is performed using the trajectory of recipes upon the identified semiconductor devices.
In another aspect of the present invention, an apparatus is provided for implementing programmed latency for improved wafer-to-wafer uniformity. The apparatus of the present invention comprises: means for identifying semiconductor devices for wafer-by-wafer analysis; means for identifying at least one value of a controlled variable in said wafer-by-wafer analysis; means for creating a trajectory of recipes for said identified semiconductor devices; means for performing a sequence analysis of wafer-to-wafer variations using said trajectory of recipes upon said identified semiconductor devices; means for performing latency control in response to said sequence analysis; and means for performing a feed-forward implementation of wafer-by-wafer latency control using said trajectory of recipes upon said identified semiconductor devices.